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HPCA
2004
IEEE
14 years 10 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti
ICPP
2002
IEEE
14 years 2 months ago
Power Aware Scheduling for AND/OR Graphs in Multi-Processor Real-Time Systems
Power aware computing has become popular recently and many techniques have been proposed to manage the energy consumption for traditional real-time applications. We have previousl...
Dakai Zhu, Nevine AbouGhazaleh, Daniel Mossé...
OOPSLA
2009
Springer
14 years 4 months ago
Parallel programming with object assemblies
We present Chorus, a high-level parallel programming model suitable for irregular, heap-manipulating applications like mesh refinement and epidemic simulations, and JChorus, an i...
Roberto Lublinerman, Swarat Chaudhuri, Pavol Cern&...
HPCA
2000
IEEE
14 years 2 months ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
ICS
1998
Tsinghua U.
14 years 2 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...