195 search results - page 23 / 39 » Fault Analysis of DPA-Resistant Algorithms |
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
IFIP
2004
Springer
14 years 26 days ago
2004
Springer
This paper focuses on the usability of the PINPAS tool. The PINPAS tool is an instruction-level interpreter for smartcard assembler languages, augmented with facilities to study si...
ISCAS
2003
IEEE
14 years 23 days ago
2003
IEEE
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems of the ...
JSA
2007
13 years 7 months ago
2007
— Hardware implementations of cryptographic algorithms are vulnerable to fault analysis attacks. Methods based on traditional fault-tolerant architectures are not suited for prot...
EUROPAR
2009
Springer
13 years 5 months ago
2009
Springer
Unstructured overlay networks for peer-to-peer applications combined with stochastic algorithms for clustering and resource location are attractive due to low-maintenance costs and...