153 search results - page 10 / 31 » Fault Tolerance Evaluation Using Two Software Based Fault In... |
TCAD
2010
13 years 3 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
ET
2008
13 years 8 months ago
2008
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
ICRE
1998
IEEE
14 years 25 days ago
1998
IEEE
Model checking is shown to be an effective tool in validating the behavior of a fault tolerant embedded spacecraft controller. The case study presented here at by judiciously abst...
ISCA
1999
IEEE
14 years 26 days ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
SIGSOFT
2008
ACM
14 years 9 months ago
2008
ACM
Exception handling is one of the popular means used for improving dependability and supporting recovery in the ServiceOriented Architecture (SOA). This practical experience paper ...