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» Fault Tolerance for Multistage Interconnection Networks
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IPPS
1998
IEEE
14 years 3 days ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
INFOCOM
2007
IEEE
14 years 2 months ago
Constructions of Fault Tolerant Linear Compressors and Linear Decompressors
— The constructions of optical buffers is one of the most critically sought after optical technologies in all-optical packet-switched networks, and constructing optical buffers d...
Cheng-Shang Chang, Tsz-Hsuan Chao, Jay Cheng, Duan...
CIC
2004
109views Communications» more  CIC 2004»
13 years 9 months ago
Fault-Tolerant Networks for Electronic Textiles
Given the dynamic and harsh environments of electronic textile applications, particularly wearable computers and large-scale sensor networks, fault-tolerance is necessary. The inte...
Zahi Nakad, Mark T. Jones, Thomas Martin
TCAD
2010
105views more  TCAD 2010»
13 years 2 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
DSN
2006
IEEE
14 years 1 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...