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MSS
2003
IEEE
113views Hardware» more  MSS 2003»
14 years 3 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong
PARELEC
2006
IEEE
14 years 4 months ago
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments
Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decre...
Bernhard Fechner
FGCS
2008
140views more  FGCS 2008»
13 years 10 months ago
Blocking vs. non-blocking coordinated checkpointing for large-scale fault tolerant MPI Protocols
A long-term trend in high-performance computing is the increasing number of nodes in parallel computing platforms, which entails a higher failure probability. Fault tolerant progr...
Darius Buntinas, Camille Coti, Thomas Hérau...
IPPS
1999
IEEE
14 years 2 months ago
Fully-Scalable Fault-Tolerant Simulations for BSP and CGM
In this paper we consider general simulations of algorithms designed for fully operational BSP and CGM machines on machines with faulty processors. The faults are deterministic (i...
Sung-Ryul Kim, Kunsoo Park
PVM
2007
Springer
14 years 4 months ago
Using CMT in SCTP-Based MPI to Exploit Multiple Interfaces in Cluster Nodes
Many existing clusters use inexpensive Gigabit Ethernet and often have multiple interfaces cards to improve bandwidth and enhance fault tolerance. We investigate the use of Concurr...
Brad Penoff, Mike Tsai, Janardhan R. Iyengar, Alan...