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» Fault simulation of interconnect opens in digital CMOS circu...
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ITC
1995
IEEE
122views Hardware» more  ITC 1995»
13 years 11 months ago
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A nalog circuit implementations of fuzzy logic are characterized by performing logical connectives of analog signals. They can be considered as generalization of digital circuits ...
Stefan Weiner
ISCAS
2003
IEEE
90views Hardware» more  ISCAS 2003»
14 years 23 days ago
A reduction technique of large scale RCG interconnects in complex frequency domain
High frequency digital LSIs usually consist of many subcircuits coupled with multi-conductor interconnects embedded in the substrate. They sometimes cause serious problems of the ...
Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hatto...
VTS
2000
IEEE
114views Hardware» more  VTS 2000»
13 years 12 months ago
Detection of CMOS Defects under Variable Processing Conditions
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, the power supply transient...
Amy Germida, James F. Plusquellic
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
14 years 23 days ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...
DAC
2005
ACM
14 years 8 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...