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» Fault simulation on reconfigurable hardware
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ATS
1998
IEEE
76views Hardware» more  ATS 1998»
14 years 1 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 3 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
VTS
1999
IEEE
83views Hardware» more  VTS 1999»
14 years 1 months ago
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
Philip P. Shirvani, Edward J. McCluskey
AHS
2007
IEEE
252views Hardware» more  AHS 2007»
14 years 3 months ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
ERSA
2006
150views Hardware» more  ERSA 2006»
13 years 10 months ago
An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator
Reconfigurable computing offers an attractive solution to accelerating infrared scene simulations. In infrared scene simulations, the modeling of a number of atmospheric and optic...
Vinay Sriram, David Kearney