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ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
CLUSTER
2004
IEEE
13 years 7 months ago
MPI/FT: A Model-Based Approach to Low-Overhead Fault Tolerant Message-Passing Middleware
Fault tolerance in parallel systems has traditionally been achieved through a combination of redundancy and checkpointing methods. This notion has also been extended to message-pas...
Rajanikanth Batchu, Yoginder S. Dandass, Anthony S...
IPPS
1998
IEEE
13 years 12 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
PDP
1996
IEEE
13 years 11 months ago
Application-Dependent Performability Evaluation of Fault-Tolerant Multiprocessors
A case study of performance and dependability evaluation of fault-tolerant multiprocessors is presented. Two specific architectures are analyzed taking into account system functio...
Stefan Dalibor, A. Hein, Wolfgang Hohl
ISORC
2007
IEEE
14 years 1 months ago
Exploiting Tuple Spaces to Provide Fault-Tolerant Scheduling on Computational Grids
Scheduling tasks on large-scale computational grids is difficult due to the heterogeneous computational capabilities of the resources, node unavailability and unreliable network ...
Fábio Favarim, Joni da Silva Fraga, Lau Che...