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IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
ICPP
1996
IEEE
13 years 12 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
ICPADS
2005
IEEE
14 years 1 months ago
2005
IEEE
Low energy consumptions are extremely important in real-time embedded systems, and scheduling is one of the techniques used to obtain lower energy consumptions. In this paper, we ...
SPAA
1995
ACM
13 years 11 months ago
1995
ACM
Many high-level parallel programming languages allow for fine-grained parallelism. As in the popular work-time framework for parallel algorithm design, programs written in such lan...
EUROPAR
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents the integration of a multi-level scheduler in the YML architecture. It demonstrates the advantages of this architecture based on a component model and why it is...