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EUROPAR
2010
Springer
13 years 7 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
SIGOPSE
2000
ACM
13 years 12 months ago
Congestion prices as feedback signals: an approach to QoS management
Recently there has been a renewed interest in the application of economic models to the management of computational resources. Most of this interest is focused on pricing models f...
Rolf Neugebauer, Derek McAuley
CDC
2008
IEEE
142views Control Systems» more  CDC 2008»
14 years 1 months ago
A LPV approach to control and real-time scheduling codesign: Application to a robot-arm control
— This paper deals with real-time control under computational constraints. A robust control approach to control/real-time scheduling co-design is proposed using the H∞ framewor...
Olivier Sename, Daniel Simon, Mongi Ben Gaid
HPCA
2004
IEEE
14 years 7 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
Todd E. Ehrhart, Sanjay J. Patel
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen