96 search results - page 16 / 20 » Feedback Scheduling for Pipelines of Tasks |
RTSS
2006
IEEE
14 years 1 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
CDC
2009
IEEE
14 years 5 days ago
2009
IEEE
Abstract— This paper presents a novel, computationally feasible procedure for computing optimal switching surfaces, i.e. optimal feedback controllers for switched autonomous nonl...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
The algorithms in the current sequential numerical linear algebra libraries (e.g. LAPACK) do not parallelize well on multicore architectures. A new family of algorithms, the tile a...
TVLSI
2008
13 years 7 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...