1563 search results - page 68 / 313 » Flexible instruction processors |
IEEEPACT
1999
IEEE
14 years 2 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
CF
2007
ACM
14 years 1 months ago
2007
ACM
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
SASP
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract—Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must ta...
FPL
2005
Springer
14 years 3 months ago
2005
Springer
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
IPPS
2006
IEEE
14 years 4 months ago
2006
IEEE
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...