1563 search results - page 73 / 313 » Flexible instruction processors |
DSD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
CSSE
2008
IEEE
14 years 28 days ago
2008
IEEE
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
GLVLSI
2008
IEEE
14 years 5 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
APCSAC
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
CODES
2005
IEEE
14 years 4 months ago
2005
IEEE
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...