Sciweavers

161 search results - page 23 / 33
» Floorplanning with Datapath Optimization
Sort
View
IPPS
2009
IEEE
14 years 5 months ago
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements
— As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and...
Tung Thanh Hoang, Magnus Själander, Per Larss...
ERSA
2008
185views Hardware» more  ERSA 2008»
14 years 10 days ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
ISSS
1996
IEEE
134views Hardware» more  ISSS 1996»
14 years 3 months ago
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
Miguel Miranda, Francky Catthoor, Martin Janssen, ...
ICCD
2000
IEEE
79views Hardware» more  ICCD 2000»
14 years 7 months ago
Efficient Logic Optimization Using Regularity Extraction
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
Thomas Kutzschebauch
ICS
1989
Tsinghua U.
14 years 2 months ago
Control flow optimization for supercomputer scalar processing
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...
Pohua P. Chang, Wen-mei W. Hwu