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» Formal Analysis of Processor Timing Models
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ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 5 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
ESTIMEDIA
2006
Springer
14 years 4 days ago
Loop Nest Splitting for WCET-Optimization and Predictability Improvement
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
Heiko Falk, Martin Schwarzer
CF
2006
ACM
14 years 2 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
SPAA
1996
ACM
14 years 18 days ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
14 years 1 days ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...