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ARTS
1997
Springer
13 years 11 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
FASE
2004
Springer
14 years 27 days ago
Checking Absence of Illicit Applet Interactions: A Case Study
Abstract. This paper presents the use of a method – and its corresponding tool set – for compositional verification of applet interactions on a realistic industrial smart card...
Marieke Huisman, Dilian Gurov, Christoph Sprenger,...
LPAR
2005
Springer
14 years 1 months ago
Pushdown Module Checking
Model checking is a useful method to verify automatically the correctness of a system with respect to a desired behavior, by checking whether a mathematical model of the system sat...
Laura Bozzelli, Aniello Murano, Adriano Peron
IJSEKE
2011
165views more  IJSEKE 2011»
12 years 11 months ago
Model Checking for Verification of Mandatory Access Control Models and Properties
rather wide gap in abstraction between policies and mechanisms. In this paper, we propose a general approach for property verification for MAC models. The approach defines a stan...
Vincent C. Hu, D. Richard Kuhn, Tao Xie, JeeHyun H...
JSA
2008
131views more  JSA 2008»
13 years 7 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...