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JSA
2008
131views more  JSA 2008»
13 years 6 months ago
Formal verification of ASMs using MDGs
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
Amjad Gawanmeh, Sofiène Tahar, Kirsten Wint...
APSEC
2009
IEEE
13 years 4 months ago
A Formal Framework to Integrate Timed Security Rules within a TEFSM-Based System Specification
Abstract--Formal methods are very useful in software industry and are becoming of paramount importance in practical engineering techniques. They involve the design and the modeling...
Wissam Mallouli, Amel Mammar, Ana R. Cavalli
SAFECOMP
2007
Springer
14 years 25 days ago
Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts
With the rapid progress in science and technology, we find ubiquitous use of safety-critical systems in avionics, consumer electronics, and medical instruments. In such systems, u...
Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen
ECBS
2010
IEEE
224views Hardware» more  ECBS 2010»
14 years 1 months ago
Timed Automata Model for Component-Based Real-Time Systems
—One of the key challenges in modern real-time embedded systems is safe composition of different software components. Formal verification techniques provide the means for design...
Georgiana Macariu, Vladimir Cretu
HASE
2007
IEEE
13 years 10 months ago
Validation Support for Distributed Real-Time Embedded Systems in VDM++
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...