575 search results - page 47 / 115 » Formal Coverification of Embedded Systems Using Model Checki... |
CAV
1999
Springer
14 years 22 days ago
1999
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. A computation that violates a general linea...
MKWI
2008
13 years 10 months ago
2008
: The advent of regulatory compliance requirements such as Sarbanes Oxley Act has forced enterprises to set up a process for managing an effective internal controls system on busin...
ATVA
2006
Springer
14 years 6 days ago
2006
Springer
In many safety-critical applications of embedded systems, the system dynamics exhibits hybrid behaviors. To enable automatic analysis of these embedded systems, many analysis tools...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
AIME
2007
Springer
14 years 2 months ago
2007
Springer
Medical critiquing systems criticise clinical actions performed by a physician. In order to provide useful feedback, an important task is to find differences between the actual a...