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DAC
2012
ACM
12 years 17 days ago
Improving gate-level simulation accuracy when unknowns exist
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
Kai-Hui Chang, Chris Browy
ICFP
2012
ACM
12 years 17 days ago
Proof-producing synthesis of ML from higher-order logic
The higher-order logic found in proof assistants such as Coq and various HOL systems provides a convenient setting for the development and verification of pure functional program...
Magnus O. Myreen, Scott Owens
ICSE
2008
IEEE-ACM
14 years 11 months ago
A verification system for timed interval calculus
Timed Interval Calculus (TIC) is a highly expressive set-based notation for specifying and reasoning about embedded real-time systems. However, it lacks mechanical proving support...
Chunqing Chen, Jin Song Dong, Jun Sun 0001
SIGSOFT
2008
ACM
14 years 11 months ago
Requirements engineering: from craft to discipline
Getting the right software requirements under the right environment assumptions is a critical precondition for developing the right software. This task is intrinsically difficult....
Axel van Lamsweerde
SIGSOFT
2007
ACM
14 years 11 months ago
SLEDE: lightweight verification of sensor network security protocol implementations
Finding flaws in security protocol implementations is hard. Finding flaws in the implementations of sensor network security protocols is even harder because they are designed to p...
Youssef Hanna