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BIRTHDAY
2010
Springer
13 years 9 months ago
Formal Semantics of a VDM Extension for Distributed Embedded Systems
Abstract. To support model-based development and analysis of embedded systems, the specification language VDM++ has been extended with asynchronous communication and improved timin...
Jozef Hooman, Marcel Verhoef
FORMATS
2007
Springer
14 years 12 days ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
HICSS
2009
IEEE
151views Biometrics» more  HICSS 2009»
14 years 3 months ago
Integrating Formal Analysis and Design to Preserve Security Properties
The use of formal methods has long been advocated in the development of secure systems. Yet, methods for deriving design from requirements that guarantee retention of the intended...
Riham Hassan, Shawn A. Bohner, Sherif El-Kassas, M...
COMCOM
1998
117views more  COMCOM 1998»
13 years 8 months ago
Specification, validation, and verification of time-critical systems
In this paper, we propose a new formalism, named the Timed Communicating Finite State Machine (Timed CFSM), for specifying and verifying time-critical systems. Timed CFSM preserve...
Shiuh-Pyng Shieh, Jun-Nan Chen
ISOLA
2010
Springer
13 years 6 months ago
Analysing Message Sequence Graph Specifications
We give a detailed construction of a finite-state transition system for a com-connected Message Sequence Graph. Though this result is fairly well-known in the literature there has...
Joy Chakraborty, Deepak D'Souza, K. Narayan Kumar