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SPIN
2000
Springer
13 years 11 months ago
The Temporal Rover and the ATG Rover
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
Doron Drusinsky
FORTE
1997
13 years 9 months ago
Automatic Checking of Aggregation Abstractions Through State Enumeration
c Checking of Aggregation Abstractions Through State Enumeration Seungjoon Park, Member, IEEE, Satyaki Das, and David L. Dill, Member, IEEE —Aggregation abstraction is a way of d...
Seungjoon Park, Satyaki Das, David L. Dill
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 8 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
COMPSEC
2008
111views more  COMPSEC 2008»
13 years 7 months ago
An ontology-based policy for deploying secure SIP-based VoIP services
-- Voice services over Internet Protocol (VoIP) are nowadays much promoted by telecommunication and Internet service providers. However, the utilization of open networks, like the ...
Dimitris Geneiatakis, Costas Lambrinoudakis, Georg...
CADE
2008
Springer
14 years 8 months ago
Certifying a Tree Automata Completion Checker
Tree automata completion is a technique for the verification of infinite state systems. It has already been used for the verification of cryptographic protocols and the prototyping...
Benoît Boyer, Thomas Genet, Thomas P. Jensen