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» Formal Techniques for Java-Like Programs
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SAC
2010
ACM
15 years 3 days ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
SAS
2010
Springer
121views Formal Methods» more  SAS 2010»
15 years 19 days ago
Alternation for Termination
Proving termination of sequential programs is an important problem, both for establishing the total correctness of systems and as a component of proving more general termination an...
William R. Harris, Akash Lal, Aditya V. Nori, Srir...
EMSOFT
2010
Springer
15 years 7 days ago
Semantics-preserving implementation of synchronous specifications over dynamic TDMA distributed architectures
We propose a technique to automatically synthesize programs and schedules for hard real-time distributed (embedded) systems from synchronous data-flow models. Our technique connec...
Dumitru Potop-Butucaru, Akramul Azim, Sebastian Fi...
PLDI
2012
ACM
13 years 4 months ago
Fully automatic and precise detection of thread safety violations
Concurrent, object-oriented programs often use thread-safe library classes. Existing techniques for testing a thread-safe class either rely on tests using the class, on formal spe...
Michael Pradel, Thomas R. Gross
ATVA
2005
Springer
130views Hardware» more  ATVA 2005»
15 years 7 months ago
Approximate Reachability for Dead Code Elimination in Esterel
Esterel is an imperative synchronous programming language for the design of reactive systems. Esterel extends Esterel with a noninstantaneous jump instruction (compatible with conc...
Olivier Tardieu, Stephen A. Edwards