726 search results - page 75 / 146 » Formal Verification and Validation of Interactive Systems Sp... |
150
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BIRTHDAY
2007
Springer
15 years 8 months ago
2007
Springer
Well understood methods exist for developing programs from formal specifications. Not only do such methods offer a precise check that certain sorts of deviations from their specifi...
184
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DLT
2009
15 years 2 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
140
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DT
2000
15 years 4 months ago
2000
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
154
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FMICS
2006
Springer
15 years 8 months ago
2006
Springer
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
147
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POPL
2010
ACM
16 years 1 months ago
2010
ACM
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...