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HASE
1999
IEEE
13 years 12 months ago
Model Checking UML Statechart Diagrams Using JACK
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
Stefania Gnesi, Diego Latella, Mieke Massink
ACSD
2004
IEEE
118views Hardware» more  ACSD 2004»
13 years 11 months ago
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Fur...
CADE
2007
Springer
14 years 8 months ago
A History-based Verification of Distributed Applications
Safety and security guarantees for individual applications in general depend on assumptions on the given context provided by distributed instances of operating systems, hardware pl...
Bruno Langenstein, Andreas Nonnengart, Georg Rock,...
TSE
1998
176views more  TSE 1998»
13 years 7 months ago
Constructive Protocol Specification Using Cicero
—New protocols are often useful, but are hard to implement well. Protocol synthesis is a solution, but synthesized protocols can be slow. Implementing protocols will be even more...
Yen-Min Huang, Chinya V. Ravishankar
WSC
2008
13 years 10 months ago
PLCStudio: Simulation based PLC code verification
Proposed in this paper is the architecture of a PLC programming environment that enables a visual verification of PLC programs. The proposed architecture integrates a PLC program ...
Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeu...