Abstract. The paper introduces the construct of temporal testers as a compositional basis for the construction of automata corresponding to temporal formulas in the PSL logic. Temp...
Studying industrial systems by simulation enables the designer to study the dynamic behaviour and to determine some characteristics of the system. Unfortunately, simulation also h...
A typical problem formal verification faces is the size of the model of a system being verified. Even for a small system, the state space of the model tends to grow exponentially (...
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
Venkita Subramonian, Christopher D. Gill, Cé...
Abstract. This paper presents an approach for formalizing the RM-ODP (Reference Model for Open Distributed Processing), an ISO and ITU standard. The goal of this formalization is t...
Andrey Naumenko, Alain Wegmann, Guy Genilloud, Wil...