Sciweavers

714 search results - page 9 / 143
» Formal Verification of Cognitive Models
Sort
View
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
14 years 9 days ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
ESORICS
2000
Springer
14 years 1 days ago
Verification of a Formal Security Model for Multiapplicative Smart Cards
Abstract. We present a generic formal security model for operating systems of multiapplicative smart cards. The model formalizes the main security aspects of secrecy, integrity, se...
Gerhard Schellhorn, Wolfgang Reif, Axel Schairer, ...
RTS
2008
131views more  RTS 2008»
13 years 8 months ago
Formal verification of multitasking applications based on timed automata model
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
Libor Waszniowski, Zdenek Hanzálek
ICESS
2005
Springer
14 years 1 months ago
Formalization of fFSM Model and Its Verification
PeaCE(Ptolemy extension as a Codesign Environment) was developed for the hardware and software codesign framework which allows us to express both data flow and control flow. The fF...
Sachoun Park, Gihwon Kwon, Soonhoi Ha
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
14 years 13 days ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim