48 search results - page 9 / 10 » Formal Verification of Diagnosability via Symbolic Model Che... |
TSE
2008
13 years 7 months ago
2008
We propose an interface specification language based on grammars for modular software model checking. In our interface specification language, component interfaces are specified a...
CHARME
2003
Springer
13 years 11 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
ACSD
2001
IEEE
13 years 11 months ago
2001
IEEE
We present a new way to define the semantics of imperative synchronous languages by means of separating the control and the data flow. The control flow is defined by predicates th...
BCS
2008
13 years 9 months ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
POPL
2005
ACM
14 years 7 months ago
2005
ACM
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...