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» Formal Verification of Gate-Level Computer Systems
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DSN
2004
IEEE
13 years 11 months ago
Assured Reconfiguration of Embedded Real-Time Software
It is often the case that safety-critical systems have to be reconfigured during operation because of issues such as changes in the system's operating environment or the fail...
Elisabeth A. Strunk, John C. Knight
DAC
2007
ACM
13 years 11 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
JAIR
2008
123views more  JAIR 2008»
13 years 7 months ago
CTL Model Update for System Modifications
Model checking is a promising technology, which has been applied for verification of many hardware and software systems. In this paper, we introduce the concept of model update to...
Yan Zhang, Yulin Ding
CCS
2008
ACM
13 years 9 months ago
Reducing protocol analysis with XOR to the XOR-free case in the horn theory based approach
In the Horn theory based approach for cryptographic protocol analysis, cryptographic protocols and (Dolev-Yao) intruders are modeled by Horn theories and security analysis boils d...
Ralf Küsters, Tomasz Truderung
FM
2009
Springer
134views Formal Methods» more  FM 2009»
13 years 5 months ago
Partial Order Reductions Using Compositional Confluence Detection
Abstract. Explicit state methods have proven useful in verifying safetycritical systems containing concurrent processes that run asynchronously and communicate. Such methods consis...
Frédéric Lang, Radu Mateescu