176 search results - page 25 / 36 » Formal Verification of Gate-Level Computer Systems |
EICS
2009
ACM
14 years 2 months ago
2009
ACM
Smart environments (e.g., airports, hospitals, stadiums, and other physical spaces using ubiquitous computing to empower many mobile people) provide novel challenges for usability...
HICSS
2008
IEEE
14 years 2 months ago
2008
IEEE
Object-oriented analysis suggests semiformal usecase driven techniques for problem domain modeling from a computation independent viewpoint. The proposed approach called Topologic...
DLT
2009
13 years 5 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
SPIN
2000
Springer
13 years 11 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
WWW
2004
ACM
14 years 8 months ago
2004
ACM
Security remains a major roadblock to universal acceptance of the Web for many kinds of transactions, especially since the recent sharp increase in remotely exploitable vulnerabil...