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» Formal Verification of Gate-Level Computer Systems
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PLDI
2010
ACM
13 years 11 months ago
Bringing Extensibility to Verified Compilers
Verified compilers, such as Leroy's CompCert, are accompanied by a fully checked correctness proof. Both the compiler and proof are often constructed with an interactive proo...
Zachary Tatlock, Sorin Lerner
COORDINATION
2009
Springer
14 years 8 months ago
Mobility Models and Behavioural Equivalence for Wireless Networks
In protocol development for wireless systems, the choice of appropriate mobility models describing the movement patterns of devices has long been recognised as a crucial factor for...
Jens Chr. Godskesen, Sebastian Nanz
CMSB
2006
Springer
13 years 11 months ago
Probabilistic Model Checking of Complex Biological Pathways
Abstract. Probabilistic model checking is a formal verification technique that has been successfully applied to the analysis of systems from a broad range of domains, including sec...
John Heath, Marta Z. Kwiatkowska, Gethin Norman, D...
APSCC
2008
IEEE
13 years 9 months ago
Contract-Based Security Monitors for Service Oriented Software Architecture
Monitors have been used for real-time systems to ensure proper behavior; however, most approaches do not allow for the addition of relevant fields required to identify and react t...
Alexander M. Hoole, Issa Traoré
ECAI
2006
Springer
13 years 9 months ago
Solving Optimization Problems with DLL
Propositional satisfiability (SAT) is a success story in Computer Science and Artificial Intelligence: SAT solvers are currently used to solve problems in many different applicati...
Enrico Giunchiglia, Marco Maratea