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» Formal Verification of Gate-Level Computer Systems
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IJNSEC
2010
145views more  IJNSEC 2010»
13 years 2 months ago
Formal Specification of Common Criteria Based Access Control Policy Model
One of the major threats that an enterprise Information system networks are facing today is the Insider threat. As part of the Insider Threat study, lack of an effective access co...
Manpreet Singh, Manjeet S. Patterh
ICCS
2007
Springer
14 years 1 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
IJIT
2004
13 years 9 months ago
Formal Verification of a Multicast Protocol In Mobile Networks
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
Mohammad Reza Matash Borujerdi, S. M. Mirzababaei
FORTE
1994
13 years 8 months ago
An improvement in formal verification
Critical safety and liveness properties of a concurrent system can often be proven with the help of a reachability analysis of a finite state model. This type of analysis is usual...
Gerard J. Holzmann, Doron Peled
DAC
2000
ACM
14 years 8 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...