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» Formal Verification of Gate-Level Computer Systems
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IC3
2009
13 years 5 months ago
Verification of Liveness Properties in Distributed Systems
Abstract. This paper presents liveness properties that need to be preserved by Event-B models of distributed systems. Event-B is a formal technique for development of models of dis...
Divakar Yadav, Michael Butler
COMCOM
1998
117views more  COMCOM 1998»
13 years 7 months ago
Specification, validation, and verification of time-critical systems
In this paper, we propose a new formalism, named the Timed Communicating Finite State Machine (Timed CFSM), for specifying and verifying time-critical systems. Timed CFSM preserve...
Shiuh-Pyng Shieh, Jun-Nan Chen
ICFEM
1997
Springer
13 years 11 months ago
Formally Specifying and Verifying Real-Time Systems
A real-time computer system is a system that must perform its functions within specified time bounds. These systems are generally characterized by complex interactions with the en...
Richard A. Kemmerer
ACSC
2004
IEEE
13 years 11 months ago
Formalization of UML Statechart Models Using Concurrent Regular Expressions
The Unified Modeling Language (UML) is widely used in the software development process for specification of system based on the object-oriented paradigm. Thought the current versi...
S. Jansamak, A. Surarerks
ISORC
1998
IEEE
13 years 11 months ago
Compositional Specification and Structured Verification of Hybrid Systems in cTLA
Many modern chemical plants have to be modelled as complex hybrid systems consisting of various continuous and event-discrete components. Besides of the modular and easy-to-read s...
Peter Herrmann, Günter Graw, Heiko Krumm