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» Formal Verification of Safety Properties in Timed Circuits
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POPL
2006
ACM
14 years 8 months ago
Formal certification of a compiler back-end or: programming a compiler with a proof assistant
This paper reports on the development and formal certification (proof of semantic preservation) of a compiler from Cminor (a Clike imperative language) to PowerPC assembly code, u...
Xavier Leroy
FDL
2007
IEEE
13 years 11 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
SIGSOFT
2006
ACM
14 years 8 months ago
SYNERGY: a new algorithm for property checking
We consider the problem if a given program satisfies a specified safety property. Interesting programs have infinite state spaces, with inputs ranging over infinite domains, and f...
Bhargav S. Gulavani, Thomas A. Henzinger, Yamini K...
DAC
2009
ACM
14 years 8 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
PPOPP
2009
ACM
14 years 8 months ago
Formal verification of practical MPI programs
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...
Anh Vo, Sarvani S. Vakkalanka, Michael Delisi, Gan...