216 search results - page 12 / 44 » Formal Verification of Safety Properties in Timed Circuits |
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
VMCAI
2010
Springer
14 years 4 months ago
2010
Springer
In the recent years, there have been a large amount of investigations on safety verification of uncertain continuous systems. In engineering and applied mathematics, this verificat...
ISCAS
2003
IEEE
14 years 26 days ago
2003
IEEE
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
Abstract. We describe how the PVS verification system has been used to verify a safety property of a garbage collection algorithm, originally suggested by Ben-Ari. The safety prope...
TCAD
2002
13 years 7 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...