216 search results - page 22 / 44 » Formal Verification of Safety Properties in Timed Circuits |
CAV
2004
Springer
14 years 29 days ago
2004
Springer
—We introduce a new BDD-like data structure called Hybrid-Restriction Diagrams (HRDs) for the representation and manipulation of linear hybrid automata (LHA) state-spaces and pre...
ICSE
1999
IEEE-ACM
13 years 11 months ago
1999
IEEE-ACM
Formal verification methods are used only sparingly in software development. The most successful methods to date are based on the use of model checking tools. To use such he user ...
CORR
2010
Springer
13 years 5 months ago
2010
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. We present a simple method for verifying the safety properties of cache coherence protocols with arbitrarily many nodes. Our presentation begins with two examples. The fi...
POPL
2000
ACM
13 years 11 months ago
2000
ACM
Various code certification systems allow the certification and static verification of important safety properties such as memory and control-flow safety. These systems are valuabl...