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» Formal Verification of Safety Properties in Timed Circuits
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ARTS
1997
Springer
13 years 11 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
ICFP
2005
ACM
14 years 7 months ago
Modular verification of concurrent assembly code with dynamic thread creation and termination
Proof-carrying code (PCC) is a general framework that can, in principle, verify safety properties of arbitrary machine-language programs. Existing PCC systems and typed assembly l...
Xinyu Feng, Zhong Shao
CHARME
2003
Springer
110views Hardware» more  CHARME 2003»
13 years 11 months ago
Exact and Efficient Verification of Parameterized Cache Coherence Protocols
Abstract. We propose new, tractably (in some cases provably) efficient algorithmic methods for exact (sound and complete) parameterized reasoning about cache coherence protocols. F...
E. Allen Emerson, Vineet Kahlon
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
14 years 1 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
DSN
2004
IEEE
13 years 11 months ago
Assured Reconfiguration of Embedded Real-Time Software
It is often the case that safety-critical systems have to be reconfigured during operation because of issues such as changes in the system's operating environment or the fail...
Elisabeth A. Strunk, John C. Knight