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» Formal Verification of Safety Properties in Timed Circuits
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ICALP
1994
Springer
13 years 11 months ago
Liveness in Timed and Untimed Systems
When provingthe correctness of algorithmsin distributed systems, one generally considers safety conditions and liveness conditions. The Input Output I O automaton model and its ti...
Rainer Gawlick, Roberto Segala, Jørgen F. S...
ECAI
2000
Springer
13 years 12 months ago
Autosteve: Automated Electrical Design Analysis
AutoSteve performs automated electrical design based on qualitative simulation and functional abstraction. It is the first commercial product capable of performing these tasks for ...
Chris Price
AMAST
2008
Springer
13 years 9 months ago
Evolving Specification Engineering
Abstract. The motivation for this work is to support a natural separation of concerns during formal system development. In a developmentby-refinement context, we would like to be a...
Dusko Pavlovic, Peter Pepper, Douglas R. Smith
UML
2001
Springer
13 years 12 months ago
Formalization of UML-Statecharts
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
Michael von der Beeck
RE
2010
Springer
13 years 2 months ago
Domain Engineering with Event-B: Some Lessons We Learned
Domain modeling is an important aspect of software engineering. This paper presents our experience of modeling land transportation domain in the formal framework of Event-B. The do...
Atif Mashkoor, Jean-Pierre Jacquot