216 search results - page 27 / 44 » Formal Verification of Safety Properties in Timed Circuits |
LPAR
2010
Springer
13 years 5 months ago
2010
Springer
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for temporal synthesis, l...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
RTS
2006
13 years 7 months ago
2006
Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. C...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...