216 search results - page 28 / 44 » Formal Verification of Safety Properties in Timed Circuits |
CAV
2007
Springer
14 years 1 months ago
2007
Springer
In 2005 we proposed the first efficient on-the-fly algorithm for solving games based on timed game automata with respect to reachability and safety properties. The first prototy...
ATVA
2006
Springer
13 years 9 months ago
2006
Springer
Abstract. In this paper, we give an algorithm for fault-tolerant proactive leader election in asynchronous shared memory systems, and later its formal verification. Roughly speakin...
DLT
2009
13 years 5 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
ENTCS
2006
13 years 7 months ago
2006
Component based development is a promising approach for embedded systems. Typical for embedded software is the presence of resource constraints in multiple dimensions. An essentia...
ENTCS
2006
13 years 7 months ago
2006
Bounded Model Checking (BMC) searches for counterexamples to a property with a bounded length k. If no such counterexample is found, k is increased. This process terminates when ...