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» Formal Verification of Safety Properties in Timed Circuits
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RV
2010
Springer
220views Hardware» more  RV 2010»
13 years 5 months ago
Runtime Verification with the RV System
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
Patrick O'Neil Meredith, Grigore Rosu
FMCAD
2006
Springer
13 years 11 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
PADS
2009
ACM
14 years 2 months ago
An Approach for Validation of Semantic Composability in Simulation Models
Semantic composability aims to ensure that the composition of simulation components is meaningful in terms of their expressed behavior, and achieves the desired objective of the n...
Claudia Szabo, Yong Meng Teo
POPL
2007
ACM
14 years 7 months ago
Variance analyses from invariance analyses
An invariance assertion for a program location is a statement that always holds at during execution of the program. Program invariance analyses infer invariance assertions that ca...
Josh Berdine, Aziem Chawdhary, Byron Cook, Dino Di...
DAC
2009
ACM
14 years 8 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke