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» Formal Verification of Safety Properties in Timed Circuits
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EMSOFT
2008
Springer
13 years 9 months ago
Disassembling real-time fault-tolerant programs
We focus on decomposition of hard-masking real-time faulttolerant programs (where safety, timing constraints, and liveness are preserved in the presence of faults) that are design...
Borzoo Bonakdarpour, Sandeep S. Kulkarni, Anish Ar...
SIGSOFT
2005
ACM
14 years 8 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...
ICSE
2009
IEEE-ACM
13 years 5 months ago
Architecting Robustness and Timeliness in a New Generation of Aerospace Systems
Aerospace systems have strict dependability and real-time requirements, as well as a need for flexible resource reallocation and reduced size, weight and power consumption. To cope...
José Rufino, João Craveiro, Paulo Ve...
FORMATS
2010
Springer
13 years 5 months ago
Robust Satisfaction of Temporal Logic over Real-Valued Signals
Abstract. We consider temporal logic formulae specifying constraints in continuous time and space on the behaviors of continuous and hybrid dynamical system admitting uncertain par...
Alexandre Donzé, Oded Maler
ASPDAC
2005
ACM
99views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Implication of assertion graphs in GSTE
- We address the problem of implication of assertion graphs that occur in generalized symbolic trajectory evaluation (GSTE). GSTE has demonstrated its powerful capacity in formal v...
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu S...