216 search results - page 43 / 44 » Formal Verification of Safety Properties in Timed Circuits |
CADE
2005
Springer
14 years 7 months ago
2005
Springer
We describe an algorithm for deciding the first-order multisorted theory BAPA, which combines 1) Boolean algebras of sets of uninterpreted elements (BA) and 2) Presburger arithmeti...
CAV
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. Regular model checking is a form of symbolic model checking technique for systems whose states can be represented as finite words over a finite alphabet, where regular ...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
Parameterized model checking refers to any method that extends traditional, finite-state model checking to handle systems arbitrary number of processes. One popular approach to thi...
HASKELL
2009
ACM
14 years 2 months ago
2009
ACM
We address the problem of reasoning about Haskell programs that use Software Transactional Memory (STM). As a motivating example, we consider Haskell code for a concurrent non-det...
Publication
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized ha...