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» Formal Verification of an Optimizing Compiler
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CASES
2010
ACM
15 years 1 months ago
Instruction selection by graph transformation
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome...
Sebastian Buchwald, Andreas Zwinkau
113
Voted
JOT
2006
113views more  JOT 2006»
15 years 3 months ago
Constraint Validation in Model Compilers
Model transformation has become one of the most focused research field, motivated by for instance the OMG's Model-Driven Architecture (MDA). Metamodeling is a central techniq...
László Lengyel, Tihamer Levendovszky...
114
Voted
FMCAD
2000
Springer
15 years 6 months ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...
FDL
2008
IEEE
15 years 5 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
ICCTA
2007
IEEE
15 years 7 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...