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» Formal Verification of an Optimizing Compiler
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SAC
2010
ACM
13 years 4 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...
IFL
2003
Springer
128views Formal Methods» more  IFL 2003»
13 years 12 months ago
With-Loop Scalarization - Merging Nested Array Operations
Construction of complex array operations by composition of more basic ones allows for abstract and concise specifications of algorithms. Unfortunately, na¨ıve compilation of suc...
Clemens Grelck, Sven-Bodo Scholz, Kai Trojahner
POPL
2010
ACM
14 years 4 months ago
A simple, verified validator for software pipelining
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Jean-Baptiste Tristan, Xavier Leroy
FMCO
2009
Springer
130views Formal Methods» more  FMCO 2009»
13 years 4 months ago
Interleaving Symbolic Execution and Partial Evaluation
Partial evaluation is a program specialization technique that allows to optimize programs for which partial input is known. We show that partial evaluation can be used with advanta...
Richard Bubel, Reiner Hähnle, Ran Ji
PLDI
2010
ACM
13 years 9 months ago
DRFX: a simple and efficient memory model for concurrent programming languages
The most intuitive memory model for shared-memory multithreaded programming is sequential consistency (SC), but it disallows the use of many compiler and hardware optimizations th...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...