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HASE
1999
IEEE
13 years 11 months ago
Model Checking UML Statechart Diagrams Using JACK
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
Stefania Gnesi, Diego Latella, Mieke Massink
FOSSACS
2008
Springer
13 years 9 months ago
Robust Analysis of Timed Automata via Channel Machines
Whereas formal verification of timed systems has become a very active field of research, the idealised mathematical semantics of timed automata cannot be faithfully implemented. Se...
Patricia Bouyer, Nicolas Markey, Pierre-Alain Reyn...
TC
2008
13 years 7 months ago
Implementing Synchronous Models on Loosely Time Triggered Architectures
Synchronous systems offer clean semantics and an easy verification path at the expense of often inefficient implementations. Capturing design specifications as synchronous models a...
Stavros Tripakis, Claudio Pinello, Albert Benvenis...
RV
2010
Springer
153views Hardware» more  RV 2010»
13 years 5 months ago
Run-Time Verification of Networked Software
Most applications that are in use today inter-operate with other applications, so-called peers, over a network. The analysis of such distributed applications requires that the effe...
Cyrille Valentin Artho
PTS
2000
99views Hardware» more  PTS 2000»
13 years 8 months ago
Verification of Test Suites
We present a formal approach to check the correctness and to propose corrections of hand-written test suites with respect to a formal specification of the protocol implementations ...
Claude Jard, Thierry Jéron, Pierre Morel