Sciweavers

294 search results - page 3 / 59
» Formal Verification of the Implementability of Timing Requir...
Sort
View
ICCS
2007
Springer
14 years 1 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
CAV
1994
Springer
111views Hardware» more  CAV 1994»
13 years 11 months ago
Automatic Verification of Timed Circuits
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
Tomas Rokicki, Chris J. Myers
CAV
2007
Springer
227views Hardware» more  CAV 2007»
13 years 11 months ago
The TASM Toolset: Specification, Simulation, and Formal Verification of Real-Time Systems
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
Martin Ouimet, Kristina Lundqvist
ICSE
2008
IEEE-ACM
14 years 8 months ago
A verification system for timed interval calculus
Timed Interval Calculus (TIC) is a highly expressive set-based notation for specifying and reasoning about embedded real-time systems. However, it lacks mechanical proving support...
Chunqing Chen, Jin Song Dong, Jun Sun 0001
FM
2009
Springer
146views Formal Methods» more  FM 2009»
13 years 5 months ago
Verifying Real-Time Systems against Scenario-Based Requirements
Abstract. We propose an approach to automatic verification of realtime systems against scenario-based requirements. A real-time system is modeled as a network of Timed Automata (TA...
Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen, S...