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FMCAD
2000
Springer
13 years 11 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
SEFM
2005
IEEE
14 years 29 days ago
From RT-LOTOS to Time Petri Nets New Foundations for a Verification Platform
The formal description technique RT-LOTOS has been selected as intermediate language to add formality to a real-time UML profile named TURTLE. For this sake, an RT-LOTOS verificat...
Tarek Sadani, Pierre de Saqui-Sannes, Jean-Pierre ...
SIGSOFT
2005
ACM
14 years 8 months ago
Reasoning about confidentiality at requirements engineering time
Growing attention is being paid to application security at requirements engineering time. Confidentiality is a particular subclass of security concerns that requires sensitive inf...
Renaud De Landtsheer, Axel van Lamsweerde
ISSTA
1998
ACM
13 years 11 months ago
Improving Efficiency of Symbolic Model Checking for State-Based System Requirements
We present various techniques for improving the time and space efficiency of symbolic model checking for system requirements specified as synchronous finite state machines. We use...
William Chan, Richard J. Anderson, Paul Beame, Dav...
FORMATS
2004
Springer
13 years 11 months ago
Decomposing Verification of Timed I/O Automata
This paper presents assume-guarantee style substitutivity results for the recently published timed I/O automaton modeling framework. These results are useful for decomposing verifi...
Dilsun Kirli Kaynar, Nancy A. Lynch