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» Formal analysis of hardware requirements
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DATE
2000
IEEE
87views Hardware» more  DATE 2000»
14 years 3 months ago
Test Synthesis for Mixed-Signal SOC Paths
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
14 years 3 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
14 years 3 months ago
Symbolic functional and timing verification of transistor-level circuits
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
Clayton B. McDonald, Randal E. Bryant
ITC
1994
IEEE
90views Hardware» more  ITC 1994»
14 years 2 months ago
Defect Classes - An Overdue Paradigm for CMOS IC
: The IC test industry has struggled .for more than 30years to establish a test approach that would guarantee a low defect level to the customer. Wepropose a comprehensive strategy...
Charles F. Hawkins, Jerry M. Soden, Alan W. Righte...
ISARCS
2010
188views Hardware» more  ISARCS 2010»
14 years 2 months ago
Component Behavior Synthesis for Critical Systems,
Abstract. Component-based architectures are widely used in embedded systems. For managing complexity and improving quality separation of concerns is one of the most important princ...
Tobias Eckardt, Stefan Henkler