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» Formal analysis of hardware requirements
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NGITS
1999
Springer
14 years 2 months ago
From Object-Process Diagrams to a Natural Object-Process Language
As the requirements for system analysis and design become more complex, the need for a natural, yet formal way of specifying system analysis findings and design decisions are becom...
Mor Peleg, Dov Dori
BMCBI
2006
141views more  BMCBI 2006»
13 years 10 months ago
Visual setup of logical models of signaling and regulatory networks with ProMoT
Background: The analysis of biochemical networks using a logical (Boolean) description is an important approach in Systems Biology. Recently, new methods have been proposed to ana...
Julio Saez-Rodriguez, Sebastian Mirschel, Rebecca ...
CAV
2009
Springer
212views Hardware» more  CAV 2009»
14 years 11 months ago
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
We present the key ideas in the design and implementation of Beaver, an SMT solver for quantifier-free finite-precision bit-vector logic (QF BV). Beaver uses an eager approach, enc...
Susmit Jha, Rhishikesh Limaye, Sanjit A. Seshia
CAV
1999
Springer
125views Hardware» more  CAV 1999»
14 years 2 months ago
Model Checking of Safety Properties
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. A computation that violates a general linea...
Orna Kupferman, Moshe Y. Vardi
ACSD
2004
IEEE
118views Hardware» more  ACSD 2004»
14 years 2 months ago
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Fur...