34 search results - page 6 / 7 » Formal hardware verification by integrating HOL and MDG |
ACSD
2006
IEEE
13 years 9 months ago
2006
IEEE
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
ATVA
2006
Springer
13 years 9 months ago
2006
Springer
Abstract. In this paper, we give an algorithm for fault-tolerant proactive leader election in asynchronous shared memory systems, and later its formal verification. Roughly speakin...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
The extensional theory of arrays is one of the most important ones for applications of SAT Modulo Theories (SMT) to hardware and software verification. Here we present a new T-solv...
FMICS
2010
Springer
13 years 7 months ago
2010
Springer
We investigate the application of the software bounded model checking tool CBMC to the domain of wireless sensor networks (WSNs). We automatically generate a software behavior mode...